Various systems have been developed and implemented to match the explosive demand for wireless communication. Such systems include cordless telephone systems, cellular mobile radio systems, public packet radio data networks, and radio paging systems. As outlined in commonly assigned Ariyavisitakul et al U.S. Pat. No. 5,084,891, Jan. 28, 1992 ("Patent '891"), the disclosure of which is incorporated by reference herein, these systems are each characterized by various advantages and drawbacks.
Among such other wireless communication systems, low power digital systems have been developed which support low-speed, portable use (for example, by pedestrians). Similar to cellular radio, low power portable digital telephony uses a fixed base unit, referred to as a radio port (RP), and a number of fixed or portable transceivers (hereinafter referred to as subscriber units (SUs)) that can simultaneously access that port on a multiplexed basis.
Low power multiplexed radio links commonly operate on a time division multiplexed/time division multiple access basis to provide a number of separate fully duplex demand-assigned digital channels between an RP and each of its associated SUs. Each RP transmits time division multiplexed bit streams on a pre-defined carrier frequency. In turn, each SU that accesses an RP responds by transmitting a TDMA burst on a common, pre-defined carrier frequency that may be different from that used by the RP (in the case of frequency-division duplexed systems), or that may be the same as that used by the RP (in the case of time-division duplexed systems). The power used by the transmitter in the SU may range between 5-10 milliwatts or less on average and provide a range of several hundred to a thousand feet. With this transmission range, an RP might simultaneously serve 20 to 30 separate locally situated SUs.
In such a system, the same TDM channels may be re-used at RPs that are spaced sufficiently far apart to reduce co-channel interference to an acceptably low level, but yet conserve valuable spectrum. To provide access to the wireline telephone network, each RP may be interfaced, typically through a conventional fixed distribution facility, over either a copper or fiber connection to a switching machine at a local central office. The switching machine is suitably programmed, in a similar manner as is a Mobile Telephone Switching Office (MTSO), to controllably and automatically handoff calls from one RP to another as subscribers move their SUs from RP to RP.
PACS (Personal Access Communication Systems) is a standard which supports low power, portable digital communication. As illustrated in FIG. 1, PACS architecture consists of four main components: the SU (portable 2 or fixed 4), the RPs 6 which are connected to a radio port control unit (RPCU) 8 and an access manager (AM) 10. An interface A, the air interface, provides a connection between the SU and the RP. Interface P provides the protocols required to connect the SUs through the RPs to the RPCU.
With PACS, a large number of radio frequency (RF) channels may be frequency division multiplexed with 80 MHz separation, or time division multiplexed. A variant of PACS, known as PACS-UB and developed for the unlicensed U.S. PCS band between 1920 and 1930 MHz, uses time division duplexing. While the present invention applies equally to frequency- and time-division duplexed systems, without loss of generality, the following material will consider only frequency-division duplexed link examples, for simplicity and clarity.
FIG. 2A shows the forward link (or downlink) from an RP to an SU. One 2.5 ms frame corresponds to eight 312.5 .mu.s time slots. Each time slot consists of 120 bits. The first 14 bits form a synchronization channel and the next ten bits form a system signaling logical channel called the Slow Channel. The Frame Synchronization Channel and the Slow Channel are used to derive initial frame synchronization for each SU. User information is transmitted in the Fast Channel which comprises the next 80 bits. The next 15 bits are used for a cyclic redundancy check for error detection, while the last bit, known as the power control bit, provides an indication to the SU to adjust its transmitting power up or down.
FIG. 2B illustrates the reverse link (or uplink) from the SUs to an RP. Again, each 2.5 ms frame is divided into eight 312.5 .mu.s time slots during which 120 bits are transmitted. The first twelve bits form a guard channel, while the next two bits enable differential encoding. This guard channel is used to prevent different TDMA bursts that are transmitting from different SUs from overlapping in time as a result, for example, of propagation delays. The SU does not actually begin transmission of the uplink burst until the differential encode bits.
As in the forward link, the next ten bits correspond to the Slow Channel, and data is contained in the next eighty bits. The next fifteen bits are used for error detection, while the last bit serves as a pad bit to provide an even number of bits for transmission.
The frequency band for PACS is 1850 MHz to 1910 MHz (uplink) paired with 1930 MHz to 1990 MHz (downlink), the "Broadband PCS Spectrum" allocated by the U.S. FCC in June 1994. As known in the art, PACS utilizes .pi./4-shifted, differential quadrature phase shift keying (DQPSK) in which the digital bit stream is separated into two binary streams before the bits are differentially encoded. Typically, this is done by directly mapping pairs of input bits onto relative phase increments of .+-.(.pi./4) and .+-.(3.pi./4) of the baseband signal.
As explained in greater detail in Patent '891, one crucial function required in TDM/TDMA systems such as PACS is the need to achieve synchronization between an RP and its associated SU. In particular, three levels of synchronization are needed: frame, burst and symbol synchronization.
Frame synchronization is necessary for an SU to determine the start of a frame and the occurrence of its currently assigned TDM/TDMA channel therein. In a frequency-division duplexed system, frame synchronization is readily achieved in an SU by having the RP continuously transmit in a TDM mode during which a known framing sequence, including "idle" information in idle TDM channels, would be transmitted at a known time relative to the start of each frame. The SU would extract frame timing of its associated RP by using a digital correlator to reset a frame counter whenever the framing sequence was received. Once frame timing is determined, the SU would then expect to receive successively occurring TDM packets arriving within a designated time window that is sufficiently wide to allow for slippage due to frequency drift.
Knowledge of time boundaries between successive .pi./4-shifted DQPSK symbol transmissions is important to obtain good radio link performance. Symbol synchronization is needed to determine the start of a data symbol situated within any transmitted TDM packet or TDMA data burst. Symbol synchronization can be derived from the received data as an integral part of the demodulation process, for example, as disclosed in Chuang et al U.S. Pat. No. 4,941,155, Jul. 10, 1990. While it will be understood that a particular application of this invention to radio transceivers may require the recovery of symbol timing for proper operation, specific details of the symbol synchronization process are known in the art and therefore are beyond the scope of this disclosure.
Burst synchronization is necessary to ensure that an SU is able to discern when it should transmit a TDMA burst in response to a TDM packet received from the RP and that both the RP and SU are able to discern which specific bit in each received TDMA burst or TDM packet, respectively, is the first bit therein. Unfortunately, each TDM packet transmitted from an RP to an associated SU is subject to timing misalignment. In the SU, this misalignment can arise from frequency drift. Burst misalignment can arise in an RP from the different propagation time delays associated with the SUs transmitting to that RP, frequency drift of local oscillators and reference oscillator error in an RP receiver. Burst misalignment can be large after an outage. Due to the need to detect and properly compensate for bit slippage arising from misaligned bursts or packets, burst and packet synchronization is difficult and complex to achieve and maintain over a sufficiently wide range of slippage, especially when the use of overhead bits for such synchronization is not feasible due to link efficiency considerations.
Apart from synchronization, a second crucial function needed in TDMA is error detection--the ability of both an RP and an SU to reliably determine whether the bit stream in any received TDM packet or TDMA burst contains an erroneous bit. Bits are frequently corrupted through interference and/or noise. If an erroneous bit occurs, then the packet or burst containing that bit needs to be blanked. With high probability the receiver should be able to detect this condition and implement appropriate recovery mechanisms.
Error detection is conventionally achieved by adding one or more parity bits to each data word to form a codeword. In its simplest form, parity takes the form of one bit that represents odd/even parity. In sophisticated forms, multiple parity bits are used to store a cyclical redundancy check (CRC). Codes for CRC generation have the desirable property that even multiple bit errors, up to a maximum number which depends on the particular code selected, will not result in the transmitted codeword being changed to another codeword. This characteristic allows a receiver to detect an error condition in which up to the maximum number of bit errors have occurred. Further, even where the number of bit errors exceeds this maximum number, with a good choice of code there is a high probability that the error in transmission will be detected. Codes that have low probability of undetected error are crucial to robust performance of wireless communication links.
Patent '891 describes a technique for bit synchronization and error detection of received digital data bursts in a TDM/TDMA system which addresses the concerns described above. This technique is believed to have broad applicability to radio link signal processing required by contemporary digital wireless technologies. In particular, the current U.S. JTC Standards (soon to be ANSI standards) for the PACS and PACS-UB air interfaces require the use of a particular channel code for error detection that is also amenable to bit synchronization in the manner described in the aforementioned patent.
As described in Patent '891, a codeword from an error detecting code is to be located and decoded within a (larger) window of demodulated bits (the "burst window"). It is assumed that the bits on either side of the codeword do not carry information pertinent to the established link and can therefore be discarded by the receiver. Prior to transmission, the first and last bits of this codeword are inverted in order to enable the synchronization capabilities of the code. As long as the received codeword falls wholly within the demodulation window, and in addition, the codeword falls within a maximum distance from a "reference" position, then the codeword can be successfully decoded in the absence of radio link errors caused by noise or interference. FIG. 4, which illustrates possible alignments for received codewords in a demodulated burst, shows this maximum distance.
In FIG. 4, times t.sub.1 and t.sub.2 delineate a reference codeword position. A first burst 42 illustrates a maximum retard codeword position which begins prior to time t.sub.1 and ends prior to time t.sub.2. A second burst 44 illustrates a reference codeword position which falls within times t.sub.1 and t.sub.2. A third burst 46 illustrates a maximum advance codeword position 46 which begins subsequent to time t.sub.1 and ends subsequent to time t.sub.2.
The maximum synchronization distance is determined by the number of CRC bits according to the following formula: EQU d.sub.max .ltoreq.floor[(n-k-2)/2]
where n is the codeword size, k is the information sequence size, and the floor function returns the largest integer not greater than its argument. For PACS, a (105, 90) cyclic codeword may be used wherein n is 105 and k is 90. Thus, (n-k)=15, so the maximum synchronization distance is 6 bits.
A block diagram of an encoder circuit that implements the channel code required by the PACS and PACS-UB standards for transmission of a TDM or TDMA burst is illustrated in FIG. 3. In this example, the encoder circuit calculates fifteen parity bits for each 90-bit informational bit stream for subsequent inclusion in a TDM bit stream using the g(x) generator specified by a polynomial equation for a corresponding cyclic code. The channel encoder appends the resulting parity bits to that informational bit stream to form a cyclic codeword and modifies the resulting cyclic codeword to include the first set of marker bits.
As shown in FIG. 3, information bits appearing on line 383 to be transmitted are sent to the modulation circuitry in the RP's or SU's transmission chain through multiplexer 340, line 345, adder 360, and line 387. The information bits are also simultaneously sent into a feedback shift register circuit 330 that calculates the CRC bits for error detection by dividing the information bits by a predetermined polynomial generator g(x) which is suitable for the PACS codeword size and information sequence size.
In this example, the g(x) divider encoder circuit 330 comprises a series arrangement of D type flip flops 331.sub.1 to 331.sub.8, where reference numeral 731.sub.1 refers to a series arrangement of six D type flip flops while reference numerals 331.sub.2 and 331.sub.4 each represents a series arrangement of two D type flip flops. Adders 332.sub.1 to 332.sub.7 combine the respective outputs of flip flops 331.sub.1 to 331.sub.8 to form the divided output bit stream. The reset input to all the D type flip flops is connected to CLEAR lead 352 from the clocking and control circuit 350 which generates its clock and control signals based upon the occurrence of each pulse in the burst timing signal appearing on lead 381. As shown, a feedback line 337 from flip flop 331.sub.8 leads to adder 310.
The bit stream received by the g(x) divider encoder circuit 330 at adder 310 is provided along lead 315 to an input A of multiplexer 326. Operating under a control signal provided from line 354 to an input C, the multiplexer 326 provides the bit stream to the input of the first set of flip flops 331.sub.1 in the g(x) divider encoder circuit. When the last information bit for the current TDM or TDMA burst is shifted into the divider circuit 330 in this manner, the flip-flop elements 331.sub.1 through 331.sub.8 will contain the CRC bits, which are the remainder of the polynomial division of the information sequence by the code's generator polynomial g(x). The multiplexer 340 then selects the shift register contents appearing at its input B, which are then shifted out to the modulation circuitry to complete the burst. The full codeword is the concatenation of the information bits (including both the Slow and Fast Channels in PACS and PACS-UB) and the CRC bits.
The first and last bits of the codeword are inverted with adder 360 by a marker sequence generated by the clocking and control circuit 350. For example, the adder 360 may comprise an XOR gate which receives a logic one signal along line 356 as the first and last bits in the codeword are received from the multiplexer 340. In this way synchronization properties referred to above are obtained.
A prior art technique for decoding a received codeword is explained in greater detail in reference to FIG. 5. This technique is based on that described in detail in Patent '891. As shown, incoming bit stream data entering the circuit from the demodulator first encounters the synchronization circuitry 100. The first and last bits of a reference codeword position are inverted at a binary adder 120 by a marker sequence generated by clock and control circuitry 180. The marked demodulated bit sequence is then circularly rotated by a prescribed amount in a gated shift register circuit 125, and the resulting marked and rotated sequence enters another shift register circuit 130 that effects a division operation by the code's generator polynomial g(x). The syndrome sequence that is produced by the divider circuit 130 will, in the absence of transmission errors, uniquely identify the position of the received codeword with respect to the reference position. This translates directly into a fixed amount of delay that must be inserted in order to align the position of the received codeword with the reference codeword position for further processing by the error detection circuitry 150.
While the synchronization syndrome is being calculated in the g(x) divider 130, the demodulated burst contents are stored in a burst buffer 105. After the synchronization syndrome is calculated, the demodulated bit stream is delivered to shift register 110, which can effect a range of fixed delays by varying the "tap point" where data is pulled out through multiplexer 115. The tap point is chosen through a synchronization syndrome lookup table 135. Since negative delay cannot be created, it is established that the reference codeword position corresponds to an intermediate delay through the shift register 110. Therefore, if the codeword is in fact found at the maximum retard codeword position, for example, as shown in FIG. 4, it can be advanced relative to the reference position by taking it through multiplexer 115 at the earliest tap point, which corresponds to zero shift register delay (i.e., for shift register 110). Similarly, a codeword found at the maximum advance position will result in a choice of shift register tap point that effects maximum delay through the shift register 110, in order to retard the received codeword timing to match the reference position.
Once the received codeword has been aligned with a reference position, it is ready for processing by error detection circuitry 150. A second marker sequence, aligned with the known first and last codeword bit positions, is generated by the clock and control circuitry 180 and is applied to another binary adder 151 to effect inversion of those bits. This restores the codeword to its original form prior to transmission, and allows the use of essentially standard error detection circuitry. A second g(x) divider 155, which preferably is separate from but identical to g(x) divider 130, produces an error syndrome. If the syndrome bits are all zeros, a successful decode operation is assumed to have been completed and bits are read out of a second burst buffer 165 directly for subsequent receive processing (e.g., by a speech decoder for voice service).
A codeword error is declared if either the synchronization circuitry 100 or the error detection circuitry 150 fails to produce recognizable syndrome patterns. This is accomplished with the use of a logical OR gate 170 operating on the separate sync error and error detect error flags. In the presence of a decoding error, the bits read out of burst buffer 165 can be blanked by logically AND-ing the decoded data bits with the inverted error flag.
In practice, it is found that the apparatus of FIG. 5 requires somewhat more than two bursts of latency between the incoming bit stream and the outgoing decoded data bits. This is because the syndromes generated by the g(x) dividers 130 and 155 cannot be determined until the bit stream for the entire demodulated burst is shifted through it.
In summary, the scheme described in the '891 Patent comprises two separate processing stages, one for synchronization and one for detection after the synchronization operation is complete. This scheme allows a pipelined implementation (operating at the air interface bit rate) with just over two (2) bursts of latency. When combined with the latencies introduced by burst buffering (for speech transmission), other radio link signal processing (e.g. demodulation), and wireline transmission into the public network, the overall round-trip delay for a PACS or PACS-UB system can approach 10 msec. Since the ITU-T recommends employment of echo suppression methods when the round-trip delay exceeds 10 msec, this latency may result in the need for additional echo suppression techniques. This, in turn, may lead to added costs and more complicated designs for receiver implementations. Thus, it would be desirable to reduce latency in the synchronization and error detection circuit.